0.  Author, ``Title," Publisher, Page, Year/Month, Venue. 
1.  T. Kishita, R. Kishida, and K. Kobayashi, ``Investigation of the Time-Dependent BTI-induced Degradation Distribution for Ring Oscillators in Ultra-Long-Term Stress Conditions," IEEE International Reliability Physics Symposium (IRPS), pp. P1.CR.1-P1.CR.4, 2025/04, Monterey, CA, USA. 
2.  T. Imagawa, R. Kishida, Y. Koyama, K. Kobayashi, and T. Miyoshi, ``A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment," IEEE International Conference on Quantum Computing and Engineering (QCE), pp. 539-540, 2024/09, Montreal Canada. 
3.  R. Toda, R. Kishida, K. Kobayashi, T. Matsuura, R. Miyauchi, A. Hyogo, ``An Evaluation Circuit for Hot Carrier Injection (HCI) Using Stage Switching Function," International Workshop on Post-Binary ULSI Systems (ULSIWS), p. 7, 2024/05, Brno, Czech. 
4.  R. Nagasue, I. Mizuno, R. Kishida, T. Iwata, and T. Yoshikawa, ``A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement," IEEE International Symposium on Circuits and Systems (ISCAS), ID2146.1-5, 2024/05, Sentosa Island, Singapore. 
5.  D. Kikuta, R. Kishida, and K. Kobayashi, ``Ring Oscillators with identical Circuit Structure to Measure Bias Temperature Instability," IEEE International Conference on ASIC (ASICON), D8-5, 2023/10, Nanjing, China. 
6.  W. Bae, R. Kishida, T. Matsuura, and A. Hyogo, ``Reducing One Operational Amplifer in an 8-bit Third-Order Noise-Shaping Successive Approximation Register Analog-to-Digital Converter with Error-Feedback Structure," International Conference on Analog VLSI Circuits (AVIC), pp. 1-5, 2022/10, Hybrid (Hiroshima-shi, Hiroshima, Japan/Online). 
7.  K. Takayanagi, R. Kishida, T. Matsuura, and A. Hyogo, ``Undershoot Reduction at Load Change by a Capacitor Connecting Circuit in Hysteretic DC-DC Buck Converter," International Conference on Analog VLSI Circuits (AVIC), pp. 215-219, 2021/10, Hybrid (Bordeaux, France/Online). 
8.  Y. Susa, R. Kishida, T. Matsuura, and A. Hyogo, ``Transition Response Improvement of Current Sensing Circuit Using Hysteresis Comparator in Buck-Boost Converter for Mobile Devices," International Conference on Analog VLSI Circuits (AVIC), pp. 210-214, 2021/10, Hybrid (Bordeaux, France/Online). 
9.  K. Nakamura, T. Matsuura, R. Kishida, and A. Hyogo, ``Two Stage Boost Converter with One Inductor for Energy Harvesting," International Conference on Analog VLSI Circuits (AVIC), pp. 200-203, 2021/10, Hybrid (Bordeaux, France/Online). 
10.  R. Hirai, R. Kishida, T. Matsuura, and A. Hyogo, ``An 8-bit Hybrid Analog-to-Digital Converter Combining Flash with Radix-3 and Two-bit/cycle Successive Approximation Register Analog-to-Digital Converter," International Conference on Analog VLSI Circuits (AVIC), pp. 65-70, 2021/10, Hybrid (Bordeaux, France/Online). 
11.  Y. Susa, R. Kishida, T. Matsuura, and A. Hyogo, ``Mode Transition Improvement by Adding Load Current Sensing Circuit in a Buck-Boost Converter for Mobile Devices," Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 132-136, 2021/03, Online. 
12.  K. Saito, R. Kishida, T. Matsuura, and A. Hyogo, ``A K-band High Gain Linearity Mixer with Current-Bleeding and Derivative Superposition Technique," Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 51-55, 2021/03, Online. 
13.  R. Kishida, I. Suda, and K. Kobayashi, ``Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65 nm Fully-Depleted Silicon-On-Insulator Process," IEEE International Reliability Physics Symposium (IRPS), pp. 4A.6.1-4A.6.6, 2021/03, Online. 
14.  Y. Tanaka, T. Matsuura, R. Kishida, and A. Hyogo, ``Duty Ratio and Capacitance Analysis of AC/DC Converter without Current Control Circuit," International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. O19.6.1-O19.6.2, 2019/12, Taipei, Taiwan. 
15.  Y. Unno, T. Matsuura, R. Kishida, and A. Hyogo, ``Examination of Incremental ADC with SAR ADC To Reduce Conversion Time with High Accuracy," International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. O17.4.1-O17.4.2, 2019/12, Taipei, Taiwan. 
16.  Y. Kobayashi, T. Matsuura, R. Kishida, and A. Hyogo, ``Investigation of Hybrid ADC Combined with First-Order Feedforward Incremental and SAR ADCs," International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. O17.3.1-O17.3.2, 2019/12, Taipei, Taiwan. 
17.  T. Asuke, R. Kishida, J. Furuta, and K. Kobayashi, ``Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation," IEEE International Conference on ASIC (ASICON), pp. B8.5.1-B8.5.4, 2019/11, Chongqing, China. 
18.  K. Satou, T. Matsuura, R. Kishida, and A. Hyogo, ``Cross Switch to Output Input Voltage Alternately," International Conference on Analog VLSI Circuits (AVIC), pp. AT2.1.1-AT2.1.3, 2019/10, Yilan, Taiwan. 
19.  Y. Tanaka, T. Matsuura, R. Kishida, and A. Hyogo, ``A Worldwide Input Voltage AC/DC Converter Using a Capacitor Instead of Current Control," International Conference on Analog VLSI Circuits (AVIC), pp. PM.3.1-PM.3.6, 2019/10, Yilan, Taiwan. 
20.  S. Sekine, T. Matsuura, R. Kishida, and A. Hyogo, ``Design Theory of Sub-Radix-3 SAR-ADC with C-C Ladder Based D/A Converter," International Conference on Analog VLSI Circuits (AVIC), pp. CONV.5.1-CONV.5.6, 2019/10, Yilan, Taiwan. 
21.  T. Hosaka, S. Nishizawa, R. Kishida, T. Matsumoto, and K. Kobayashi, ``Compact Modeling of NBTI Replicationg AC Stress / Recovery from a Single-shot Long-term DC Measurement," IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 305-309, 2019/07, Rhodes Island, Greece. 
22.  R. Kishida, T. Asuke, J. Furuta, and K. Kobayashi, ``Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive Ring Oscillators," IEEE International Conference on Microelectronic Test Structures (ICMTS), pp. 24-27, 2019/03, Kitakyushu, Japan. 
23.  S. Sekine, T. Matsuura, R. Kishida, and A. Hyogo, ``A Novel C-2αC Ladder Based Non-binary DAC for SAR-ADC Using Unit Capacitors," International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 457-462, 2018/11, Ishigaki, Okinawa, Japan. 
24.  R. Kudo, T. Matsuura, R. Kishida, and A. Hyogo, ``Consideration on Noise-Shaping SAR ADC in Incremental Use for High Resolution and Low Power Application," International Conference on Analog VLSI Circuits (AVIC), pp. 109-112, 2018/11, Chiang Mai, Thailand. 
25.  T. Mishiro, T. Matsuura, R. Kishida, and A. Hyogo, ``A Digital Foreground Calibration Method Using Redundancy for SAR-ADCs," International Conference on Analog VLSI Circuits (AVIC), pp. 105-108, 2018/11, Chiang Mai, Thailand. 
26.  R. Kishida, J. Furuta, and K. Kobayashi, ``Plasma Induced Damage Depending on Antenna Layers in Ring Oscillators," International Conference on Solid State Devices and Materials (SSDM), pp. 209-210, 2017/09, Sendai, Japan. 
27.  T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. Kobayashi, ``Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS," IEEE International Conference on IC Design and Technology (ICICDT), pp. I2.01-I2.04, 2017/05, Austin, TX, USA. 
28.  M. Yabuuchi, A. Oshima, T. Komawaki, R. Kishida, J. Furuta, K. Kobayashi, P. Weckx, B. Kaczer, T. Matsumoto, and H. Onodera, ``Circuit Analysis and Defect Characteristics Estimation Methods Using Bimodal Defect-Centric Random Telegraph Noise Model," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 47-52, 2017/03, Monterey, CA, USA. 
29.  R. Kishida, and K. Kobayashi, ``Degradation Caused by Negative Bias Temperature Instability Depending on Body Bias on NMOS or PMOS in 65 nm Bulk and Thin-BOX FDSOI Processes," IEEE Electron Devices Technology and Manufacturing (EDTM), pp. 122-123, 2017/03, Toyama, Japan. 
30.  R. Kishida, and K. Kobayashi, ``Correlations between Plasma Induced Damage and Negative Bias Temperature Instability in 65 nm Bulk and Thin-BOX FDSOI Processes," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 25-27, 2016/10, Burlingame, CA, USA. 
31.  R. Kishida, and K. Kobayashi, ``Negative Bias Temperature Instability by Body Bias on Ring Oscillators in Thin BOX Fully-Depleted Silicon on Insulator Process," International Conference on Solid State Devices and Materials (SSDM), pp. 711-712, 2016/09, Tsukuba, Japan. 
32.  A. Oshima, T. Komawaki, K. Kobayashi, R. Kishida, P. Weckx, B. Kaczer, T. Matsumoto, and H. Onodera, ``Physical-Based RTN Modeling of Ring Oscillators in 40-nm SiON and 28-nm HKMG by Bimodal Defect-Centric Behaviors," International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 327-330, 2016/09, Nurnberg, Germany. 
33.  R. Kishida, A. Oshima, and K. Kobayashi, ``Negative Bias Temperature Instability Caused by Plasma Induced Damage in 65 nm Bulk and Silicon On Thin BOX (SOTB) Processes," IEEE International Reliability Physics Symposium (IRPS), pp. CA.2.1-CA.2.5, 2015/04, Monterey, CA, USA. 
34.  R. Kishida, A. Oshima, M. Yabuuchi, and K. Kobayashi, ``Initial Frequency Degradation and Variation on Ring Oscillators from Plasma Induced Damage in Fully-Depleted Silicon on Insulator Process," IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), none, 2014/11, San Jose, CA, USA. 
35.  R. Kishida, A. Oshima, M. Yabuuchi, and K. Kobayashi, ``Initial and Long-Term Frequency Degradation on Ring Oscillators from Plasma Induced Damage in 65 nm Bulk and Silicon On Thin BOX processes," International Conference on Solid State Devices and Materials (SSDM), pp. 52-53, 2014/09, Tsukuba, Japan. 
36.  M. Yabuuchi, R. Kishida, and K. Kobayashi, ``Correlation between BTI-Induced Degradations and Process Variations by Measuring Frequency of RO," IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), pp. 128-131, 2014/06, Kyoto, Japan.