Research Overview
At the Accelerated Systems Research Group, we conduct systems research in computer science. In recent years, the demands placed on computers have grown ever higher — driven by AI programs that require high performance, such as large language models (LLMs) and machine learning, and by services that handle confidential information, such as financial transactions and medical-data analysis. To meet the needs of such diverse applications, we aim to realize next-generation computers that harness the latest hardware technologies — accelerators (GPUs, FPGAs, Google TPUs), high-speed networks, trusted execution environments (TEEs), and quantum computers.
In particular, we specialize in system software (operating systems) and hardware. To make the most of the latest hardware, we rethink the design and architecture of computers from the ground up, proposing, building, and verifying optimal systems from both the hardware and the system-software sides. In this way, we realize next-generation computers that are far faster, more secure, and more efficient than conventional ones.
Research Themes
To realize next-generation computers that harness emerging hardware, we work across the following five research areas, proposing, building, and evaluating optimal systems from both the hardware and the system-software sides.
Accelerator Virtualization in the Cloud and Datacenters
To handle the tens of thousands of service requests from users, cloud environments increasingly adopt accelerators — such as GPUs, FPGAs, and AI accelerators — that specialize in particular computations. Unlike general-purpose devices such as CPUs, however, cloud systems still lack the mechanisms to share accelerators among users and to use large numbers of them efficiently.
In this research, we enhance virtualization technologies such as the OS and hypervisor to build cloud infrastructures that let users and cloud services share and use diverse accelerators with high efficiency. By allocating (scheduling) the most suitable accelerators according to each service’s type and priority, we enable a wide variety of cloud services to be accelerated by hardware accelerators.
Keywords: Cloud computing, Microservices, Serverless, Virtualization, FPGA, GPU, TPU, Orchestration
Projects: Funky (SoCC'25), Proteus (EuroSys'26), F3 (HPDC'25), XPUVirt
Hardware–OS Co-design for Efficient Accelerator Control
Accelerators such as FPGAs, together with smart I/O devices that process large volumes of data at high speed (SmartNICs, SmartSSDs), promise high performance. However, because they have hardware architectures and proprietary interfaces that differ greatly from conventional devices such as CPUs, using them within existing computer systems requires more complex control.
In this research, we co-design hardware and the OS to control each accelerator and smart device efficiently and flexibly. Beyond the software layer (APIs, libraries, and the OS) that lets CPU-side applications share and use these devices, we also design dedicated hardware that controls device-side applications quickly and efficiently — achieving high throughput, low latency, and strong security together, so that applications can easily harness the latest accelerators.
Keywords: FPGA, SmartNIC, Computational storage, Operating systems, Hardware/OS co-design, I/O virtualization
Projects: vFPIO (USENIX ATC'24), μShell (OSDI'26), P2P-Accel
Security and Data Protection for Next-Generation Computers
With the rise of AI services, it has become common for computers to collect and analyze personal information such as financial data and medical records. At the same time, the cloud datacenters that now underpin most information services host tens of thousands of users sharing the same computing resources, demanding far more robust security and data-protection mechanisms.
In this research, we leverage Trusted Execution Environments (TEEs) — a hardware-based data-protection feature of modern CPUs — to build trustworthy, large-scale datacenter and network infrastructures. By redesigning TEEs, which were originally intended for CPU-side applications, so that they also apply to accelerators and smart I/O devices, we aim to realize features that solve a range of security challenges in today’s cloud — such as protecting data on accelerators and authenticating and tamper-detecting messages exchanged over the network.
Keywords: Trusted execution environments (TEEs), Trusted computing, SmartNIC, Byzantine fault tolerance, Disaggregation
Projects: TDOS (APSys'23), TNIC (ASPLOS'25), SafeBus
Next-Generation Datacenters Powered by High-Speed Networks
To transfer and process the massive amounts of data required for AI training and large-scale data analysis, modern datacenters have adopted ultra-fast networks of 400 Gbps and even 800 Gbps (40–80× the speed of 5G). However, so much data arrives at once that conventional CPUs cannot keep up: the OS that controls the network and the CPU that processes the data become bottlenecks, preventing the network from delivering its full performance.
In this research, we develop network switches and a control OS that make the most of high-speed networks. Beyond eliminating the control overhead of conventional software, we treat the entire datacenter as a single computing resource over the network — enabling efficient control of accelerators and memory distributed across the network, and large-scale computation using large numbers of GPUs.
Keywords: High-speed networking, RDMA, SmartNIC, Data centers
Projects: ReFlex, P4-OS
Error-Correcting Hardware and a Control OS for Quantum Computers
Quantum computers promise to solve, at high speed, computations that would take conventional computers an enormous amount of time. Yet their qubits are scarce and susceptible to noise, errors arise from the inherent nature of quantum systems, and quantum hardware varies greatly across implementations — leaving many challenges on the path to practical use.
In this research, we design and develop error-correcting hardware that corrects a quantum computer’s computational errors quickly at runtime, together with a control OS. Through hardware–OS co-design, we achieve stable quantum computation with fewer errors, realizing reliable and practical quantum computers.
Keywords: Quantum computing, Quantum error correction, NISQ, Hardware/OS co-design
Projects: Q-connect, Q-shell
